29 Sep 2025

STM32 103

архитектура - arm cortex, little endian

Memory map

source: https://nercury.github.io/resources/mcu-02/cortex-m-basics

• 0x00_00_00_00-0x1F_FF_FF-FF: flash память. Что интересно, содержимое доступно одновременно и c базовым адресом 0x0, и с 0x08_00_00_00. Типичный размер 64-128 КБ.
• 0x20_00_00_00-0x39_FF_FF_FF: Оперативная памяти (20-64КБ), обычно маппится в начало
• 0x40_00_00_00-0x59_FF_FF_FF: периферия, скорее всего маппится в начало
• 0xE0_00_E0_00-0xE0_00_EF_FF: “This region holds, among other things, registers related to the Nested Vectored Interrupt controller and the SysTick timer.”

source: https://blog.attify.com/analyzing-bare-metal-firmware-binaries-in-ghidra/

#define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END       0x08007FFFUL /*!< FLASH END address of bank1 */
#define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
 
#define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
 
 
/*!< Peripheral memory map */
#define APB1PERIPH_BASE       PERIPH_BASE
 
[...]
 
#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
#define FLASHSIZE_BASE        0x1FFFF7E0UL    /*!< FLASH Size register base address */
#define UID_BASE              0x1FFFF7E8UL    /*!< Unique device ID register base address */
#define OB_BASE               0x1FFFF800UL    /*!< Flash Option Bytes base address */
 
#define DBGMCU_BASE          0xE0042000UL /*!< Debug MCU registers base address */